1. Technical Field
The present invention relates to a digital processing device, more particularly to a chip having integrated multiple processor cores and to a data processing method.
2. Description of the Related Art
Among the types of digital processing devices, the portable terminal is an electronic device that is made to have a small size, to perform functions for gaming, mobile communication, etc., as well as to allow convenient carrying by a user. Different types of a portable terminal may include, for example, a mobile communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP) and an MP3 player, etc.
Here, the mobile communication terminal is basically a device implemented to enable telecommunication between persons in remote locations. By using a mobile communication terminal, it is possible for a user to telecommunicate with a remotely-located receiver even while in motion. However, thanks to developments in technology, the latest mobile communication terminal is further equipped with supplementary functions such as camera and multimedia data playback, in addition to the basic functions of voice communication, short message service, and address book.
FIG. 1 is a block diagram illustrating the composition of a mobile communication terminal equipped with a camera function according to the related art.
Referring to FIG. 1, a mobile communication terminal 100 equipped with a camera function as a supplementary function includes a high-frequency processing unit 110, an analog-to-digital converter unit 115, a digital-to-analog converter unit 120, a controller 125, a power supply unit 130, a key input unit 135, a main memory 140, a display unit 145, a camera 150, an image processing unit 155, and an auxiliary memory 160.
The high-frequency processing unit 110 processes high-frequency signals received or transmitted through an antenna.
The analog-to-digital converter unit 115 converts analog signals, inputted from the high-frequency processing unit 110, into digital signals and transfers the signals to the controller 125.
The digital-to-analog converter unit 120 converts digital signals, inputted from the controller 125, into analog signals and transfers the signals to the high-frequency processing unit 110.
The controller 125 controls the overall operation of the mobile communication terminal 100. The controller 125 may include, for example, a central processing unit (CPU) or a microcontroller.
The power supply unit 130 supplies electric power necessary for operating the mobile communication terminal 100. The power supply unit 130 can be coupled to an external power source or can include terminals for coupling to a battery, etc.
The key input unit 135 generates key data for setting various functions in the mobile communication terminal 100 or for dialing, etc., and transfers the data to the controller 125. The key input unit 135 can be implemented, for example, as a key pad that includes multiple key buttons.
The main memory 140 stores the operating system of the mobile communication terminal 100 and various data, etc. The main memory 140 can be composed of flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), etc.
The display unit 145 displays the operational status of the mobile communication terminal 100 and external images photographed using the camera 150, etc. The display unit 145 can include, for example, a liquid crystal display (LCD) panel.
The camera 150 photographs an external image (a photographic subject) and generates and outputs an image signal corresponding to the photographed external image.
The image processing unit 155 processes the image signals inputted from the camera 150. The image processing unit 155 performs such functions as color interpolation, gamma correction, image quality correction, and JPEG encoding, etc. The camera 150 and image processing unit 155 can be controlled by the controller 125.
The auxiliary memory 160 stores the external image processed by the image processing unit 155, etc.
As described above, the mobile communication terminal 100 having a camera function is equipped with multiple processor chips. That is, a main processor chip and one or more application processor chips are included. An application processor chip is controlled by the main processor chip to perform a preset supplementary function.
Referring to the mobile communication terminal 100 illustrated in FIG. 1, the mobile communication terminal 100 includes a controller 125, which is a main processor (MP) for controlling the overall functions, and an image processing unit 155, which is an application processor (AP) for controlling the camera function. As described above, the image processing unit 155 is controlled by the controller 125. The controller 125 and the image processing unit 155 are implemented as independent processors (or processor chips), and each of the processors is coupled to an independent memory.
The types of application processors, which can be implemented as independent processors and which are controlled by the main processor, may vary according to the supplementary functions equipped in the portable terminal. For example, an application processor for performing a camera function can perform such functions as JPEG encoding and JPEG decoding, etc., and an application processor for performing a video playback function can perform such functions as video file (e.g. MPEG4, DIVX, H.264), encoding and decoding, etc., while an application processor for a music file playback function can perform music file (e.g. MP3, WMA, WMV) encoding and decoding, etc.
Each of these processors is coupled individually to a memory, in order to store the processed data. Therefore, according to the related art, the greater the number of functions provided by a portable terminal, the greater must be the number of processors and the number of memories included, which as a result causes an increase in the external size of the portable terminal.
To resolve this problem, attempts are being made to have a memory shared by multiple processors (or processor chips). FIG. 2 provides an example of a connection relationship in a case where a main processor and an application processor shares a memory.
FIG. 2 is a drawing showing a coupling structure for a main processor, an application processor, a shared memory, and a display device, according to the related art.
Referring to FIG. 2, the main processor 210 and the application processor 220 exchange information through a coupled bus. Here, the exchanged information may be one or more process commands, such as a command for controlling the application processor 220, data to be processed by the application processor 220, an activate/deactivate command for the display device 240, and an instruction to process data written in the shared memory 230, for example.
In general, a bus refers to a shared-use electrical pathway used in a computer, etc., for exchanging information between a processor, a main memory device, and an input/output device. A bus includes lines for information on the address of each device or the location of a memory device, and lines for differentiating the various data transmission operations to be performed. Hereinafter, the bus that couples the main processor with the application processor 220 will be referred to as the MP-AP bus. Also, the bus that couples the main processor 210 to the shared memory will be referred to as the MP-SM bus, while the bus that couples the application processor 220 to the shared memory 230 will be referred to as the AP-SM bus.
The main processor 210 is coupled by way of the MP-SM bus to the shared memory 230, and writes certain data (e.g. display parameters, etc.) in a particular storage area of the shared memory 230 or reads the data written in a certain storage area. Here, the main processor 210 can be a processor, which controls the overall operation of the digital processing device (e.g. portable terminal) and also controls the operation of the application processor 220. The display parameters can be, for example, coordinates representing a drawing broken down into triangles as needed to display the drawing, and information on what color and effect will be rendered to the plane of the relevant triangle.
The application processor 220 is coupled by way of the AP-SM bus to the shared memory 230, and writes certain data in a particular storage area of the shared memory 230 or reads the data written in a certain storage area.
The application processor 220 can be a processor which exclusively performs a supplementary function (e.g. processing one or more of MPEG4 data processing, 3D graphics, camera functionality, MP3 file playback, etc.) according to the control of the main processor 210.
If such is the case, when a process command (e.g. a process command and process type instruction for data written in a certain address) is received through the MP-AP bus from the main processor 210, the application processor 220 accesses the shared memory 230 through the AP-SM bus, and reads the data written in the relevant storage area of the shared memory 230 (i.e. data written by the main processor 210). Here, as the main processor 210 would store the relevant data in the shared memory 230, the main processor 210 must first terminate the access to the relevant area, in order for the application processor 220 to access the relevant area.
The shared memory 230 is structured to be shared by multiple coupled processors (i.e. the main processor 210 and one or more application processors), and is equipped with access ports, the number of which equals or exceeds the number of processors to be accessed by.
Supposing that the processors sharing the shared memory 230 are one main processor 210 and one application processor 220, as illustrated in FIG. 2, the shared memory 230 must have at least two access ports 250, 255. That is, the main processor 210 may access the memory unit 260 through the MP-SM bus and a first access port 250, while the application processor 220 may access the memory unit 260 through the AP-SM bus and a second access port 255.
Each access port can be equipped with an n number of pins for exchanging address signals with corresponding processors, an m number of pins for exchanging data, and a k number of pins for exchanging control signals. Here, n, m, and k may be certain natural numbers.
FIG. 3 is a drawing illustrating the detailed compositions of the main processor and application processor in FIG. 2.
The conventional structure in which one shared memory 230 is shared by multiple processors 210, 220 includes two independent processor chips and one memory element electrically coupled together. As each processor is implemented as an independent chip, a processor and a processor chip will be used to convey the same meaning in the present disclosure.
The shared memory 230 can be connected to the internal components of each processor by way of the bus (i.e. MP-SM bus, AP-SM bus), as well as a shared memory controller 335, 365 and a system bus 330, 360 included in each processor 210, 220.
As illustrated, the main processor 210 includes an MP core (main processor core) 310, a graphic processing unit 315, a peripheral apparatus controller 320, a host interface part 325, a system bus 330, and a shared memory controller 335.
The MP core 310 controls the overall functioning of the mobile communication terminal 100. That is, it is a component that controls the overall operation of the mobile communication terminal 100, which includes various components such as the main processor 210, application processor 220, shared memory 230, etc. Thus, the MP core 310, by way of the host interface, controls the operations of other coupled application processors, and also provides control for operations based on user commands inputted using the key input unit 135.
The graphic processing unit 315 is a component which processes image data that will be displayed through the display device 240. The graphic processing unit 315 performs the process operations that have to be performed by the main processor 210, from among the various operations for processing image data that will be displayed through the display device 240. The process operations and objectives of the main processor 210 for processing the relevant image data are apparent to those skilled in the art, and thus will not be described here in further detail.
The peripheral apparatus controller 320 provides control for peripheral apparatus that require control by the main processor 210.
The process operations of the graphic processing unit 315 and peripheral apparatus controller 320 described above can be controlled by the MP core 310. Also, it is apparent that the graphic processing unit 315 and the peripheral apparatus controller 320 can be included as components of the MP core 310.
The host interface part 325 is an interfacing means for coupling the main processor 210 with the application processor 220. Based on the operation of the host interface part 325 of the main processor 210 and the operation of the host interface part 340 of the application processor 220, a host interface is set between the two. The host interface is the portion where the signals of two processors interface, and is a path for exchanging information between the main processor 210 and the application processor 220.
The system bus 330 is a means for interfacing that allows each component within the main processor 210 to communicate with one another.
The shared memory controller 335 provides control that allows particular components of the main processor 210 to access the shared memory 230 and write/read data.
The application processor 220 includes a host interface part 340, an AP core (application processor core) 345, a graphic processing unit 350, a peripheral apparatus controller 355, a system bus 360, and a shared memory controller 335.
The host interface part 340 is an interfacing means for coupling the main processor 210 with the application processor 220.
The AP core 345 performs a corresponding operation according to the control command of the MP core 310. The application processor 220 is implemented to perform a particular operation (e.g. camera function, multimedia function, etc.). The AP core 345 controls a corresponding process or controls each of the components within the application processor 220, to make it possible for the application processor 220 to perform a designated operation according to a control command from the MP core 310.
The graphic processing unit 350 is a component which processes image data that will be displayed through the display device 240. The graphic processing unit 350 performs the process operations that have to be performed by the application processor 220, from among the various operations for processing image data that will be displayed through the display device 240. For example, a process may be performed for rendering a particular effect to the relevant image, etc. The process operations and objectives of the application processor 220 for processing the relevant image data are apparent to those skilled in the art, and thus will not be described here in further detail.
The peripheral apparatus controller 355 provides control for peripheral apparatus that require control by the application processor 220.
The process operations of the graphic processing unit 350 and peripheral apparatus controller 355 described above can be controlled by the AP core 345. Also, it is apparent that the graphic processing unit 350 and the peripheral apparatus controller 355 can be included as components of the AP core 345.
The system bus 360 is a means for interfacing that allows each component within the application processor 220 to communicate with one another.
The shared memory controller 335 provides control that allows particular components of the application processor 220 to access the shared memory 230 and write/read data.
As described above with reference to FIG. 2, the main processor 210 has at least two buses for connecting to the application processor 220 and the shared memory 230, respectively, and by having the application processor 220 connect to the display device 240, the main processor 210 may control the display device 240. In other words, the main processor 210 can control which image data is to be displayed through the display device 240.
Also, in transferring data between the main processor 210 and the application processor 220, a method may be used, in which the relevant data is not transferred through the host interface but is written in the shared memory 230 for transfer, to enable a faster mode of data transfer. That is, the main processor 210 may store the data awaiting transfer in a particular location within the shared memory 230, and then transfer information on the location where the relevant is written, through the host interface to the application processor 220, at which the application processor 220 may access the relevant location and read the written data.
As described above, the conventional coupling structure illustrated in FIGS. 2 and 3 has the advantage that the role of the host interface is minimized, as the transfer path of data is set to include the shared memory 230. In other words, the host interface can be limited to serve as a transfer path for information or control commands.
Despite the advantage described above, the conventional coupling structure includes the two independent processor chips and the shared memory 230 existing independently, so that installation space for three chips is necessarily required on the PCB. This becomes a reason why the outer size of a portable terminal cannot be reduced below a certain level.
Also, from the perspective of installing, maintaining, and managing software, there is the inconvenience of having to port programs separately to each of the independent processor chips, and the problem that the software structure becomes complicated.
Furthermore, as described with reference to FIG. 3, two buses must exist independently for accessing the shared memory, while a component 335, 365 for shared memory control must exist individually in each processor chip, to present the problem of complicated communication between processors.
Moreover, in the conventional coupling structure, the internal structure of the shared memory 230 is not defined, and thus the shared memory 230 may be used inefficiently, according to which area each processor is authorized to access.